features ? built using the advantages and compatibility of cmos and ixys hdmos tm processes. ? latch up protected ? high peak output current: 9a peak ? operates from 4.5v to 35v ? -55 c to 125 c extended operating temperature standard ? ability to disable output under faults ? high capacitive load drive capability: 2500pf in <15ns ? matched rise and fall times ? low propagation delay time ? low output impedance ? low supply current applications ? driving mosfets and igbts ? motor controls ? line drivers ? pulse generators ? local power on/off switch ? switch mode power supplies (smps) ? dc to dc converters ? pulse transformer driver ? limiting di/dt under short circuit ? class d switching amplifiers first release copyright ? ixys corporation 2004 patent pending general description the ixdd409/ixdi409/ixdn409 are high speed high current gate drivers specifically designed to drive the largest mosfets and igbts to their minimum switching time and maximum practical frequency limits. the ixdd409/ixdi409/ixdn409 can source and sink 9a of peak current while producing voltage rise and fall times of less than 30ns. the input of the drivers are compatible with ttl or cmos and are fully immune to latch up over the entire operating range. designed with small internal delays, cross conduction/current shoot-through is virtually eliminated in the ixdd409/ixdi409/ixdn409. their features and wide safety margin in operating voltage and power make the drivers unmatched in performance and value. the ixdd409 incorporates a unique ability to disable the output under fault conditions. when a logical low is forced into the enable input, both final output stage mosfets (nmos and pmos) are turned off. as a result, the output of the ixdd409 enters a tristate mode and achieves a soft turn-off of the mosfet/igbt when a short circuit is detected. this helps prevent damage that could occur to the mosfet/igbt if it were to be switched off abruptly due to a dv/dt over-voltage transient. the ixdn409 is configured as a non-inverting gate driver, and the ixdi409 is an inverting gate driver. the ixdd409/ixdi409/ixdn409 are available in the standard 8-pin p-dip (pi), sop-8 (si), 5-pin to-220 (ci) and in the to-263 (yi) surface-mount packages. figure 1a - ixdd409 (non inverting with enable) diagram ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci 9 ampere low-side ultrafast mosfet driver figure 1b - ixdn409 (non-inverting) diagram figure 1c - ixdi409 (inverting) diagram part number package type temp. range configuration ixdd409pi 8-pin pdip ixdd409si 8-pin soic ixdd409yi 5-pin to-263 ixdd409ci 5-pin to-220 -55 c to +125 c non inverting with enable line ixdi409pi 8-pin pdip ixdi409si 8-pin soic IXDI409YI 5-pin to-263 ixdi409ci 5-pin to-220 -55 c to +125 c inverting ixdn409pi 8-pin pdip ixdn409si 8-pin soic ixdn409yi 5-pin to-263 ixdn409ci 5-pin to-220 -55 c to +125 c non inverting ordering information ds99054b(08/04)
2 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci unless otherwise noted, t a = 25 o c, 4.5v v cc 35v . all voltage measurements with respect to gnd. ixdd409 configured as described in test conditions . electrical characteristics symbol parameter test conditions min typ max units v ih high input voltage 4.5v v cc 18v 3.5 v v il low input voltage 4.5v v cc 18v 0.8 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh output resistance @ output high i out = 10ma, v cc = 18v 0.8 1.5 ? r ol output resistance @ output low i out = 10ma, v cc = 18v 0.8 1.5 ? i peak peak output current v cc is 18v 9 a i dc continuous output current limited by package power dissipation 2 a v en enable voltage range ixdd409 only - .3 vcc + 0.3 v v enh high en input voltage ixdd409 only 2/3 vcc v v enl low en input voltage ixdd409 only 1/3 vcc v t r rise time c l =2500pf vcc=18v 8 10 15 ns t f fall time c l =2500pf vcc=18v 8 10 15 ns t ondly on-time propagation delay c l =2500pf vcc=18v 33 36 40 ns t offdly off-time propagation delay c l =2500pf vcc=18v 31 33 36 ns t enoh enable to output high delay time ixdd409 only, vcc=18v 52 ns t dold disable to output low disable delay time ixdd409 only, vcc=18v 30 ns v cc power supply voltage 4.5 18 35 v i cc power supply current v in = 3.5v v in = 0v v in = + v cc 1 0 3 10 10 ma a a absolute maximum ratings (note 1) operating ratings specifications subject to change without notice parameter v alue supply voltage 40v all other pins -0.3v to v cc + 0.3v junction temperature 150 o c storage temperature -55 o c to 150 o c soldering lead temperature (10s) 300 o c tab temperature (10s) 260 o c thermal resistance (to ambient) 8 pin pdip (pi) ( ja ) 120 k/w 8 pin soic (sia) 110 k/w to-220 (ci) 50 k/w ja with heat sink ** heat sink area of 1 cm 2 8 pin soic 95 k/w to-263 95 k/w heat sink area of 3 cm 2 8 pin soic 85 k/w to-263 85 k/w ** device soldered to metal back pane. heat sink area is 1 oz. copper on 1 side of 0.06" thick fr4 pc board. parameter value operating temperature range -55 o c to 125 o c thermal resistance (junction to case) ( jc ) 8 pin pdip (pi) 8 pin soic (si) to-220 (ci), to-263 (yi) 2.5 k/w 70 k/w 10 k/w
3 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci pin description symbol function description vcc supply voltage positive power-supply voltage input. this pin provides power to the entire chip. the range for this voltage is from 4.5v to 35v. in input input signal-ttl or cmos compatible. en * enable the system enable pin. this pin, when driven low, disables the chip, forcing high impedance state to the output (ixdd409 only). out output driver output. for application purposes, this pin is connected, through a resistor, to gate of a mosfet/igbt. gnd ground the system ground pin. internally connected to all circuitry, this pin provides ground reference for the entire chip. this pin should be connected to a low noise analog ground plane for optimum performance. figure 2 - characteristics test diagram * this pin is used only on the ixdd409, and is n/c on the ixdi409 and ixdn409. note 1: operating the device beyond parameters with listed ?absolute maximum ratings? may cause permanent damage to the device. typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. the guaranteed specifications apply only for the test conditions listed. exposure to absolute maximum rated conditions for extended periods may affect device reliability. caution: these devices are sensitive to electrostatic discharge; follow proper esd procedures when handling and assembling this component. v in 8 pin dip (pi) so8 (si) to220 (ci) to263 (yi) vc c out gnd in e n * 1 2 3 4 5 pin configurations vcc in en * gnd vcc out gnd out 1 2 3 4 8 7 6 5
4 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci typical performance characteristics fig. 3 fig. 4 fig. 5 fig. 6 fig. 7 fig. 8 rise times vs. supply voltage 0 5 10 15 20 25 30 35 40 8 9 10 11 12 13 14 15 16 17 18 supply voltage (v) rise time (ns) 2950 p f 5860 pf 8900 pf 11900 pf 1500 pf rise time vs. load capacitance 5 10 15 20 25 30 35 1.35 2.7 5.4 8.1 10.8 load capacitance rise time (ns) 8v 10v 12v 14v 16v 1 8 v fall times vs. supply voltage 0 5 10 15 20 25 30 8 9 10 11 12 13 14 15 16 17 18 supply voltage (v) fall times (ns) 5860 pf 2950 pf 8900 pf 11900 pf 1500 pf fall time vs. load capacitance 5 7 9 11 13 15 17 19 21 23 25 1.35 2.7 5.4 8.1 10.8 load capacitance (nf) fall time (ns) 8v 10v 12v 14v 16v 1 8 v rise and fall times vs. temperature cl=2500pf, vcc=18v 0 2 4 6 8 10 12 -40-20 0 25406085 temperature time (ns) rise time fall time max / min input vs. temperature 0 0.5 1 1.5 2 2.5 3 3.5 -40-20 0 25406085 temperature max / min input (v) minimum input low maximum input high
5 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci fig. 9 fig. 10 fig. 11 fig. 12 fig. 13 fig. 14 supply current vs. load capacitance vcc = 18v 0.1 1 10 100 1000 1000 10000 load capacitance (pf) supply current (ma) 10khz 50khz 1 mhz 2 mhz 100khz 500khz supply current vs. load capacitance vcc = 12v 0.1 1 10 100 1000 1000 10000 load capacitance (pf) supply current (ma) 10khz 50khz 100khz 1mhz 2mhz 500khz supply current vs. load capacitance vcc = 8v 0.1 1 10 100 1000 1000 10000 load capacitance (pf) supply current (ma) 10khz 50khz 100khz 500khz 1mhz 2mhz supply current vs. frequency vcc = 12v 0.01 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 1350 p f 2700 p f 5400 p f 8100 p f 10800 p f supply current vs. frequency vcc = 8v 0.01 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 1350 pf 2700 pf 5400 pf 8100 pf 10800 pf supply current vs. frequency vcc = 18v 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 1350 pf 2700 pf 5400 pf 8100 pf 10800 pf
6 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci fig. 15 fig. 16 fig. 17 fig. 18 fig. 19 fig. 20 propagation delay vs. supply voltage 30 32 34 36 38 40 42 44 46 48 50 8 9 10 11 12 13 14 15 16 17 18 supply voltage (v) propagation delay (ns) tondly (dd409, dn409) toffdly (di409) toffdly(dd409, dn409) tondly (di409) propagation delay vs. input voltage 30 32 34 36 38 40 42 44 46 48 50 3456789101112 input voltage (v) propagation delay (ns) tondly (dd409, dn409) toffdly (di409) toffdly (dd409, dn409) tondly (di409) propagation delay times vs. junction temperature 0 5 10 15 20 25 30 35 40 45 -40-20 0 25406085 temperature (c) time (ns) tondly (dd409, dn409) toffdly (di409) toffdly (dd409, dn409) tondly (di409) quiescent supply current vs. junction temperature vcc=18v vin=5v@1khz 0 0.1 0.2 0.3 0.4 0.5 0.6 -40 -20 0 25 40 60 85 temperature (c) quiescent supply current (ma) vcc vs. p channel peak output current cl = 10 nf -14 -12 -10 -8 -6 -4 -2 0 5 7.5 10 12.5 15 17.5 20 22.5 25 vcc (v) p channel peak output current (a) vcc vs. n channel peak output current cl=10 nf 0 2 4 6 8 10 12 14 16 18 20 5 7.5 10 12.5 15 17.5 20 22.5 25 vcc (v) n ch anne l p ea k o utput c urrent (a)
7 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci figure 25 - typical application short circuit di/dt limit fig. 21 fig. 22 fig. 23 high state output resistance vs. supply voltage 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 5 7.5 10 12.5 15 17.5 20 22.5 25 supply voltage (v) high state output resistance (ohms) low state output resistance vs. supply voltage 0 0.2 0.4 0.6 0.8 1 1.2 5 7.5 10 12.5 15 17.5 20 22.5 25 supply voltage (v) low state output resistance (ohms) fig. 24 p channel output current vs. temperature vcc = 18v cl = 10 nf 8 8.2 8.4 8.6 8.8 9 9.2 9.4 9.6 9.8 10 -60 -40 -20 0 20 40 60 80 100 temperature (c) p ch anne l o u t pu t c urren t (a) n channel peak ouput current vs. temperature vcc = 18v cl = 10 nf 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 -60 -40 -20 0 20 40 60 80 100 temperature (c) n channel output current (a)
8 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci short circuit di/dt limit a short circuit in a high-power mosfet module such as the vm0580-02f, (580a, 200v), as shown in figure 25, can cause the current through the module to flow in excess of 1500a for 10 s or more prior to self-destruction due to thermal runaway. for this reason, some protection circuitry is needed to turn off the mosfet module. however, if the module is switched off too fast, there is a danger of voltage transients occuring on the drain due to ldi/dt, (where l represents total inductance in series with drain). if these voltage transients exceed the mosfet's voltage rating, this can cause an avalanche break- down. the ixdd409 has the unique capability to softly switch off the high-power mosfet module, significantly reducing these ldi/dt transients. thus, the ixdd409 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients. the ixdd409 is designed to not only provide 9a under normal conditions, but also to allow it's output to go into a high impedance state. this permits the ixdd409 output to control a separate weak pull-down circuit during detected overcurrent shutdown conditions to limit and separately control d vgs /dt gate turnoff. this circuit is shown in figure 26. referring to figure 26, the protection circuitry should include a comparator, whose positive input is connected to the source of the vm0580-02. a low pass filter should be added to the input of the comparator to eliminate any glitches in voltage caused by the inductance of the wire connecting the source resistor to ground. (those glitches might cause false triggering of the comparator). the comparator's output should be connected to a srff( set reset flip flop). the flip-flop controls both the enable signal, and the low power mosfet gate. please note that cmos 4000- series devices operate with a v cc range from 3 to 15 vdc, (with 18 vdc being the maximum allowable limit). a low power mosfet, such as the 2n7000, in series with a resistor, will enable the vmo580-02f gate voltage to drop gradually. the resistor should be chosen so that the rc time constant will be 100us, where "c" is the miller capacitance of the vmo580-02f. for resuming normal operation, a reset signal is needed at the srff's input to enable the ixdd409 again. this reset can be generated by connecting a one shot circuit between the ixdd409 input signal and the srff restart input. the one shot will create a pulse on the rise of the ixdd409 input, and this pulse will reset the srff outputs to normal operation. when a short circuit occurs, the voltage drop across the low- value, current-sensing resistor, (rs=0.005 ohm), connected between the mosfet source and ground, increases. this triggers the comparator at a preset level. the srff drives a low input into the enable pin disabling the ixdd409 output. the srff also turns on the low power mosfet, (2n7000). in this way, the high-power mosfet module is softly turned off by the ixdd409, preventing its destruction. applications information figure 26 - application test diagram 10uh ld 0.1ohm rd rs 20nh ls 1ohm rg 10kohm r+ vmo580-02f hi g h _ power 5kohm rcom p 100 p f c+ + - v+ v- com p lm339 1600ohm rsh ccom p 1pf vcc vcca in en gnd out ixdd409 + - vin + - vcc + - ref + - vb cd4001a nor2 1mohm ros not2 cd4049a cd4011a nand cd4049a not1 cd4001a nor1 cd4049a not3 low _ power 2n7002/plp 1pf cos 0 s r en q one shot circuit sr flip-flop gnd
9 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci when designing a circuit to drive a high speed mosfet utilizing the ixdd409/ixdi409/ixdn409, it is very important to keep certain design criteria in mind, in order to optimize performance of the driver. particular attention needs to be paid to supply bypassing , grounding , and minimizing the output lead inductance . say, for example, we are using the ixdd409 to charge a 5000pf capacitive load from 0 to 25 volts in 25ns? using the formula: i= ? v c / ? t, where ? v=25v c=5000pf & ? t=25ns we can determine that to charge 5000pf to 25 volts in 25ns will take a constant current of 5a. (in reality, the charging current won?t be constant, and will peak somewhere around 8a). supply bypassing in order for our design to turn the load on properly, the ixdd409 must be able to draw this 5a of current from the power supply in the 25ns. this means that there must be very low impedance between the driver and the power supply. the most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (these capacitors should be carefully selected, low inductance, low resistance, high-pulse current- service capacitors). lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the ixdd409 to an absolute minimum. grounding in order for the design to turn the load off properly, the ixdd409 must be able to drain this 5a of current into an adequate grounding system. there are three paths for returning current that need to be considered: path #1 is between the ixdd409 and it?s load. path #2 is between the ixdd409 and it?s power supply. path #3 is between the ixdd409 and whatever logic is driving it. all three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. in addition, every effort should be made to keep these three ground paths distinctly separate. otherwise, (for instance), the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the ixdd409. output lead inductance of equal importance to supply bypassing and grounding are issues related to the output lead inductance. every effort should be made to keep the leads between the driver and it?s load as short and wide as possible. if the driver must be placed farther than 2? from the load, then the output leads should be treated as transmission lines. in this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connect directly to the ground terminal of the load. supply bypassing and grounding practices, output lead inductance the enable (en) input to the ixdd409 is a high voltage cmos logic level input where the en input threshold is ? v cc , and may not be compatible with 5v cmos or ttl input levels. the ixdd409 en input was intentionally designed for enhanced noise immunity with the high voltage cmos logic levels. in a typical gate driver application, v cc =15v and the en input threshold at 7.5v, a 5v cmos logical high input applied to this typical ixdd409 application?s en input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. the note below is for optional adaptation of ttl or 5v cmos levels. the circuit in figure 27 alleviates this potential logic level misinterpretation by translating a ttl or 5v cmos logic input to high voltage cmos logic levels needed by the ixdd409 en input. from the figure, v cc is the gate driver power supply, typically set between 8v to 20v, and v dd is the logic power supply, typically between 3.3v to 5.5v. resistors r1 and r2 form a voltage divider network so that the q1 base is positioned at the midpoint of the expected ttl logic transition levels. a ttl or 5v cmos logic low, v ttllow =~<0.8v, input applied to the q1 emitter will drive it on. this causes the level translator output, the q1 collector output to settle to v cesatq1 + v ttllow =<~2v, which is sufficiently low to be correctly interpreted as a high voltage cmos logic low (<1/3v cc =5v for v cc =15v given in the ixdd409 data sheet.) a ttl high, v ttlhigh =>~2.4v, or a 5v cmos high, v 5vcmoshigh =~>3.5v, applied to the en input of the circuit in figure 27 will cause q1 to be biased off. this results in q1 collector being pulled up by r3 to v cc =15v, and provides a high voltage cmos logic high output. the high voltage cmos logical en output applied to the ixdd409 en input will enable it, allowing the gate driver to fully function as an 8 amp output driver. the total component cost of the circuit in figure 27 is less than $0.10 if purchased in quantities >1k pieces. it is recommended that the physical placement of the level translator circuit be placed close to the source of the ttl or cmos logic circuits to maximize noise rejection. figure 27 - ttl to high voltage cmos level translator ttl to high voltage cmos level translation (ixdd409 only) 10k r3 3.3k r2 q1 2n3904 en output cc (from gate driver power supply) input) ttl cmos 3.3k r1 v dd (from logic power supply) or high voltage (to ixdd409 en input)
10 ixdd409pi / 409si / 409yi / 409ci ixdi409pi / 409si / 409yi / 409ci ixdn409pi / 409si / 409yi / 409ci ixys semiconductor gmbh edisonstrasse15 ; d-68623; lampertheim tel: +49-6206-503-0; fax: +49-6206-503627 e-mail: marcom@ixys.de ixys corporation 3540 bassett st; santa clara, ca 95054 tel: 408-982-0700; fax: 408-496-0670 www.ixys.com e-mail: sales@ixys.net package outlines note: mounting or solder tabs on all packages are connected to ground 8-pin pdip (ixd_409pi) 8-pin sop (ixd_409si) 5-lead to-263 (ixd_409yi) 5-lead to-220 (ixd_409ci)
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